TCIC(4)

NAME
tcic - Databook TCIC-2 PCMCIA controller driver

SYNOPSIS
insmod tcic.o [pc_debug=n] [tcic_base=n] [ignore=n] [do_scan=n] [irq_list=i,j,...] [cs_irq=n] [poll_interval=n] [poll_quick=n] [cycle_time=n] [async_clock=n]

DESCRIPTION
This is the low-level driver for the Databook TCIC-2 PCMCIA interface controller. It is used by Card Services for programming the TCIC-2 chip, and for monitoring card status change events.

PARAMETERS

pc_debug=n
    Selects the PCMCIA debugging level. This parameter is only available if the module is compiled with debugging enabled. A non-zero value enables debugging.

tcic_base=n
    Sets the base I/O port address of the TCIC-2 chip. The default is 0x240.

ignore=n
    Causes the driver to ignore a single socket. Sockets are numbered starting at 0. The socket will be left in whatever state it was already in, so it can be used for cards with point enablers that do not cooperate with Card Services.

do_scan=n
    This flag specifies that all free interrupts should be tested to see if they can be triggered by the PCMCIA controller. The default is 1 (on).

irq_list=i,j,...
    Specifies the set of interrupts that may be allocated by this driver, if they are otherwise available. The default list is 3, 4, 5, 6, 7, 10, 11, and 14.

cs_irq=n
    Sets the interrupt line to use for monitoring card status changes. The default is 0, which means pick any legal interrupt not already in use. Legal values are 14, 10, 7, 6, 5, 4, and 3.

poll_interval=n
    Sets the card status polling delay, in 1/100 second increments. If this parameter is set, card status interrupts will be disabled.

poll_quick=n
    When a card status change interrupt is received, the TCIC-2 chip is briefly polled for additional status changes. This parameter sets the polling delay, in 1/100 second increments. The default is 5, meaning 0.05 seconds.

cycle_time=n
    Sets the length of a CCLK external clock cycle, in nanoseconds. The default is 70 ns, corresponding to a standard ISA 14.31818 MHz clock.

async_clock=n
    This flag specifies that PCMCIA bus cycles should be clocked asynchronously from host bus cycles, effectively adding extra wait states to some operations. The default is 0 (off).

AUTHOR
David Hinds - dhinds@allegro.stanford.edu

SEE ALSO
cardmgr(8), pcmcia(5).